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SH7708 数据表(PDF) 520 Page - Renesas Technology Corp |
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SH7708 数据表(HTML) 520 Page - Renesas Technology Corp |
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520 / 633 page  502 EXTAL input or CKIO input Stable input clock Reset or NMI interrupt request Stable input clock Normal Normal Standby PLL output, CKIO output Internal clock STATUS 0 STATUS 1 PLL synchronization Note: PLL oscillation settling time when clock is input from EXTAL pin or CKIO pin tPLL PLL synchronization Figure 17.8 PLL Synchronization Settling Time in Case of Reset or NMI Interrupt EXTAL input or CKIO input Stable input clock IRL (3–0) interrupt request Stable input clock Normal Normal PLL output, CKIO output Internal clock STATUS 0 STATUS 1 Note: PLL oscillation settling time when clock is input from EXTAL pin or CKIO pin tPLL PLL synchronization tIRLSTB Standby PLL synchronization Figure 17.9 PLL Synchronization Settling Time in Case of IRL Interrupt |
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