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SH7708 数据表(PDF) 292 Page - Renesas Technology Corp |
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SH7708 数据表(HTML) 292 Page - Renesas Technology Corp |
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292 / 633 page  274 Wait State Control: As the clock frequency increases, it becomes impossible to complete all states in one cycle as in basic access. Therefore, provision is made for state extension by using the setting bits in WCR2 and MCR. The timing with state extension using these settings is shown in figure 10.35. Additional Tpc cycles (cycles used to secure the CE precharge time) can be inserted by means of the TPC bits in MCR. The number of OE and WEn assert cycles from RAS assertion to CAS assertion can be varied between 1 and 3 according to the setting of A3W1 and A3W0 in WCR2. Trw cycles can be inserted by means of the RCD bits in MCR, and the number of cycles from CE assertion to BS assertion and write data output can be varied between 1 and 4. |
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