SH7708 datasheet(301/633 Pages) RENESAS

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10.3.8

PCMCIA Interface

In the SH7708 Series, setting the A5PCM bit in BCR1 to 1 makes the bus interface for physical

space area 5 an IC memory card interface as stipulated in JEIDA version 4.2 (PCMCIA2.1).

Setting the A6PCM bit to 1 makes the bus interface for physical space area 6 an IC memory card

and I/O card interface as stipulated in JEIDA version 4.2. When the IC memory card interface is

selected, a BCR1 register setting enables page mode burst access mode to be used. This burst

access mode is not stipulated in JEIDA version 4.2, but allows high-speed data access using ROM

provided with a burst mode, etc.

When the PCMCIA interface is used, a bus size of 8 or 16 bits can be set by bits A5SZ1 and

A5SZ0, or A6SZ1 and A6SZ0, in BCR2.

Figure 10.41 shows an example of PCMCIA card connection to the SH7708 Series. To enable

active insertion of the PCMCIA cards (i.e. insertion or removal while system power is being

supplied), a 3-state buffer must be connected between the SH7708 Series’s bus interface and the

PCMCIA cards.

As operation in big-endian mode is not explicitly stipulated in the JEIDA/PCMCIA specifications,

the PCMCIA interface for the SH7708 Series in big-endian mode is stipulated independently.

If PCMCIA is used in area 6, synchronous DRAM is used at the same time, and a synchronous

DRAM auto-refresh (CAS-before-RAS refresh) request is issued simultaneously, area 6 card

enable signals

CS6 and CE2B may be asserted earlier than usual, at the same time as the

immediately preceding auto-refresh cycle. When both PCMCIA and synchronous DRAM are

used, they should be used in area 5. When area 5 is used, the system design should provide for CS

to be asserted early without causing any problems.

SH7708 数据表(PDF) 301 Page - Renesas Technology Corp