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H8/3003 数据表(PDF) 344 Page - Renesas Technology Corp |
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H8/3003 数据表(HTML) 344 Page - Renesas Technology Corp |
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344 / 715 page  — External clock source Bits TPSC2 to TPSC0 in TCR select an external clock input pin (TCLKA to TCLKD), and its valid edge or edges are selected by bits CKEG1 and CKEG0. The rising edge, falling edge, or both edges can be selected. The pulse width of the external clock signal must be at least 1.5 system clocks when a single edge is selected, and at least 2.5 system clocks when both edges are selected. Shorter pulses will not be counted correctly. Figure 10-18 shows the timing when both edges are detected. Figure 10-18 Count Timing for External Clock Sources (when Both Edges are Detected) ø TCNT input TCNT External clock input N – 1 N N + 1 326 |
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