H8SLASH3003 datasheet(12/715 Pages) RENESAS

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11.3.2

Output Timing................................................................................................. 399

11.3.3

Normal TPC Output........................................................................................ 400

11.3.4

Non-Overlapping TPC Output........................................................................ 402

11.3.5

TPC Output Triggering by Input Capture....................................................... 404

11.4

Usage Notes .................................................................................................................... 405

11.4.1

Operation of TPC Output Pins........................................................................ 405

11.4.2

Note on Non-Overlapping Output .................................................................. 405

Section 12

Watchdog Timer ........................................................................................ 407

12.1

Overview ........................................................................................................................ 407

12.1.1

Features........................................................................................................... 407

12.1.2

Block Diagram................................................................................................ 408

12.1.3

Pin Configuration............................................................................................ 408

12.1.4

12.2

Register Descriptions...................................................................................................... 410

12.2.1

Timer Counter (TCNT)................................................................................... 410

12.2.2

Timer Control/Status Register (TCSR)........................................................... 411

12.2.3

Reset Control/Status Register (RSTCSR) ...................................................... 413

12.2.4

Notes on Register Access ............................................................................... 415

12.3

Operation ........................................................................................................................ 417

12.3.1

Watchdog Timer Operation............................................................................. 417

12.3.2

Interval Timer Operation ................................................................................ 418

12.3.3

Timing of Setting of Overflow Flag (OVF) .................................................... 419

12.3.4

Timing of Setting of Watchdog Timer Reset Bit (WRST) ............................. 420

12.4

Interrupts ........................................................................................................................ 421

12.5

Usage Notes .................................................................................................................... 421

Section 13

Serial Communication Interface........................................................... 423

13.1

Overview ........................................................................................................................ 423

13.1.1

Features........................................................................................................... 423

13.1.2

Block Diagram................................................................................................ 425

13.1.3

Input/Output Pins............................................................................................ 426

13.1.4

13.2

Register Descriptions...................................................................................................... 427

13.2.1

Receive Shift Register (RSR) ......................................................................... 427

13.2.2

Receive Data Register (RDR) ......................................................................... 427

13.2.3

Transmit Shift Register (TSR) ........................................................................ 428

13.2.4

Transmit Data Register (TDR)........................................................................ 428

13.2.5

Serial Mode Register (SMR) .......................................................................... 429

13.2.6

Serial Control Register (SCR) ........................................................................ 433

13.2.7

Serial Status Register (SSR) ........................................................................... 437

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