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H8/3003 数据表(PDF) 95 Page - Renesas Technology Corp |
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H8/3003 数据表(HTML) 95 Page - Renesas Technology Corp |
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95 / 715 page ![]() Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an interrupt mask bit. Bit 3 UE Description 0 UI bit in CCR is used as interrupt mask bit 1 UI bit in CCR is used as user bit (Initial value) Bit 2—NMI Edge Select (NMIEG): Selects the NMI input edge. Bit 2 NMIEG Description 0 Interrupt is requested at falling edge of NMI input (Initial value) 1 Interrupt is requested at rising edge of NMI input 5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) IPRA and IPRB are 8-bit readable/writable registers that control interrupt priority. 77 |
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