H8SLASH3003 datasheet(31/715 Pages) RENESAS

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Table 1-3 Pin Functions (cont)

Pin No.

Type

Symbol

QFP-112

I/O

Name and Function

Refresh

RFSH

100

Output Refresh: Indicates a refresh cycle

controller

CS3

101

Output Row address strobe

RAS: Row address

strobe signal for DRAM connected to area 3

Output Column address strobe

CAS: Column

address strobe signal for bit DRAM connected

to area 3; used with 2

WE DRAM.

Write enable: Write enable signal for DRAM

connected to area 3; used with 2

CAS DRAM.

HWR

Output Upper write: Write enable signal for DRAM

connected to area 3; used with 2

WE DRAM.

Upper column address strobe: Column

address strobe signal for DRAM connected to

area 3; used with 2

CAS DRAM.

LWR

Output Lower write: Write enable signal for DRAM

connected to area 3; used with 2

WE DRAM.

Lower column address strobe: Column

address strobe signal for DRAM connected to

area 3; used with 2

CAS DRAM.

DREQ3 to

16, 14

Input

DMA request 3 to 0: DMAC activation

DREQ0

9, 8

requests

TEND3 to

15, 13,

Output Transfer end 3 to 0: These signals indicate

TEND0

106, 105

that the DMAC has ended a data transfer

TCLKD to

108 to 105 Input

Clock input A to D: External clock inputs

TCLKA

TIOCA4 to

4, 2, 111,

Input/

Input capture/output compare A4 to A0:

TIOCA0

109, 107

output

GRA4 to GRA0 output compare or input

capture, or PWM output

TIOCB4 to

5, 3, 112,

Input/

Input capture/output compare B4 to B0:

TIOCB0

110, 108

output

GRB4 to GRB0 output compare or input

capture, or PWM output

TOCXA4

Output Output compare XA4: PWM output

TOCXB4

Output Output compare XB4: PWM output

DMA

controller

(DMAC)

16-bit

integrated

time unit

(ITU)

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