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H8/3003 数据表(PDF) 23 Page - Renesas Technology Corp |
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H8/3003 数据表(HTML) 23 Page - Renesas Technology Corp |
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23 / 715 page ![]() 1.2 Block Diagram Figure 1-1 shows an internal block diagram. Figure 1-1 Block Diagram Data bus Port 4 P5 /A P5 /A P5 /A P5 /A 7 6 5 4 23 22 21 20 A A A A A A A A A A A A A A A A A A A A 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P9 /SCK /IRQ P9 /SCK /IRQ P9 /RxD P9 /RxD P9 /TxD P9 /TxD 5 4 3 2 1 0 1 0 1 0 1 0 5 4 Port 7 Port A PC /IRQ PC /IRQ PC /DREQ /CS PC /TEND /CS PC /DREQ /CS PC /TEND /CS PC PC 7 6 7 6 7 6 5 4 1 0 3 3 2 2 5 4 3 2 Port B P8 /CS P8 /CS /IRQ P8 /CS /IRQ P8 /CS /IRQ P8 /RFSH/IRQ 40 3 2 1 0 1 2 3 3 2 1 0 P6 /BACK P6 /BREQ P6 /WAIT 2 1 0 MD MD MD EXTAL XTAL ø STBY RES RESO NMI AS RD HWR LWR 2 1 0 H8/300H CPU Clock osc. Interrupt controller RAM 512 bytes 16-bit integrated timer unit (ITU) Programmable timing pattern controller (TPC) DMA controller (DMAC) Serial communication interface (SCI) 2 channels × A/D converter Watchdog timer (WDT) Refresh controller 5 |
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