H8SLASH3003 datasheet(11/715 Pages) RENESAS

11 / 715 page

10.2.11

Timer I/O Control Register (TIOR)................................................................ 310

10.2.12

Timer Status Register (TSR)........................................................................... 312

10.2.13

Timer Interrupt Enable Register (TIER)......................................................... 315

10.3

CPU Interface ................................................................................................................. 317

10.3.1

16-Bit Accessible Registers ............................................................................ 317

10.3.2

8-Bit Accessible Registers .............................................................................. 319

10.4

Operation ........................................................................................................................ 321

10.4.1

Overview......................................................................................................... 321

10.4.2

Basic Functions............................................................................................... 322

10.4.3

Synchronization .............................................................................................. 332

10.4.4

PWM Mode .................................................................................................... 334

10.4.5

Reset-Synchronized PWM Mode ................................................................... 338

10.4.6

Complementary PWM Mode.......................................................................... 341

10.4.7

Phase Counting Mode..................................................................................... 351

10.4.8

Buffering......................................................................................................... 353

10.4.9

ITU Output Timing ......................................................................................... 360

10.5

Interrupts ........................................................................................................................ 362

10.5.1

Setting of Status Flags .................................................................................... 362

10.5.2

Clearing of Status Flags.................................................................................. 364

10.5.3

Interrupt Sources and DMA Controller Activation ........................................ 365

10.6

Usage Notes .................................................................................................................... 366

Section 11

Programmable Timing Pattern Controller ......................................... 381

11.1

Overview ........................................................................................................................ 381

11.1.1

Features........................................................................................................... 381

11.1.2

Block Diagram................................................................................................ 382

11.1.3

TPC Pins ......................................................................................................... 383

11.1.4

Registers ......................................................................................................... 384

11.2

Register Descriptions...................................................................................................... 385

11.2.1

Port A Data Direction Register (PADDR) ...................................................... 385

11.2.2

Port A Data Register (PADR) ......................................................................... 385

11.2.3

Port B Data Direction Register (PBDDR) ...................................................... 386

11.2.4

Port B Data Register (PBDR) ......................................................................... 386

11.2.5

Next Data Register A (NDRA) ....................................................................... 387

11.2.6

Next Data Register B (NDRB) ....................................................................... 389

11.2.7

Next Data Enable Register A (NDERA) ........................................................ 391

11.2.8

Next Data Enable Register B (NDERB)......................................................... 392

11.2.9

TPC Output Control Register (TPCR)............................................................ 393

11.2.10

TPC Output Mode Register (TPMR).............................................................. 396

11.3

Operation ........................................................................................................................ 398

11.3.1

Overview......................................................................................................... 398

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