H8SLASH3003 datasheet(17/715 Pages) RENESAS

17 / 715 page

Page

Item

Description

P514

17.3.2

Exit from Sleep Mode

Description amended

Exit by Interrupt

P529 to Table 18-4

Electrical Characteristics

Condition values amended

P536

to 18-8

P520 to Table 18-2

DC Characteristics

Values changed and added to table

P526

P529 to Table 18-4

Bus Timing

Values changed

P531

P532

Table 18-5

Refresh Controller Bus Timing

Values changed

P536

Table 18-8

A/D Conversion Characteristics

Values changed

P541

Figure 18-7

DRAM Bus Timing (Read/Write):

*added

Three-State Access

— 2

WE Mode —

P543

Figure 18-10 DRAM Bus Timing (Read/Write):

*added

Three-State Access

— 2

CAS Mode —

P545

Figure 18-13 PSRAM Bus Timing (Read/Write):

*added

Three-State Access

P555

Table A-1

Instruction Set

Operation amended

MOV. B Rs, @(d:16, ERd)

Table A-1

Instruction Set

Operation amended

MOV. B Rs, @(d:24, ERd)

P556

Table A-1

Instruction Set

Operation amended

MOV. W Rs, @(d:16, ERd)

Table A-1

Instruction Set

Operation and number of execution

MOV. W Rs, @(d:24, ERd)

states amended

Table A-1

Instruction Set MOV. L #xx:32, Rd Number of execution states amended

Table A-1

Instruction Set POP, L ERn

Number of execution states amended

P557

Table A-1

Instruction Set PUSH. L ERn

Number of execution states amended

P566

Table A-1

Instruction Set STC

Menmonics amended (3 places)

P575

Table A-3

Number of Cycles per Instruction

Internal operation added

BSRd:16

P673

Figure C-4

Port 7 Block Diagram (Pin P7n)

Figure amended

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