H8SLASH3003 datasheet(94/715 Pages) RENESAS

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5.2 Register Descriptions

5.2.1 System Control Register (SYSCR)

SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the

action of the UI bit in CCR, selects the NMI edge, and enables or disables the on-chip RAM.

Only bits 3 and 2 are described here. For bits 7 to 4, see section 17.2, Register Configuration.

For bit 0, see section 15.2, System Control Register (SYSCR).

SYSCR is initialized to H'0B by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit

Initial value

Read/Write

SSBY

R/W

STS2

R/W

STS1

R/W

STS0

R/W

RAME

R/W

NMIEG

R/W

—

R/W

Software standby

Standby timer

select 2 to 0

User bit enable

Selects whether to use CCR bit 6

as a user bit or interrupt mask bit

NMI edge select

Selects the NMI input edge

Reserved bit

RAM enable

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