H8SLASH3003 datasheet(13/715 Pages) RENESAS

13 / 715 page

13.2.8

Bit Rate Register (BRR) ................................................................................. 441

13.3

Operation ........................................................................................................................ 450

13.3.1

Overview......................................................................................................... 450

13.3.2

Operation in Asynchronous Mode.................................................................. 452

13.3.3

Multiprocessor Communication ..................................................................... 461

13.3.4

Synchronous Operation .................................................................................. 468

13.4

SCI Interrupts.................................................................................................................. 477

13.5

Usage Notes .................................................................................................................... 478

Section 14

A/D Converter............................................................................................ 483

14.1

Overview ........................................................................................................................ 483

14.1.1

Features........................................................................................................... 483

14.1.2

Block Diagram................................................................................................ 484

14.1.3

Input Pins ........................................................................................................ 485

14.1.4

14.2

Register Descriptions...................................................................................................... 487

14.2.1

A/D Data Registers A to D (ADDRA to ADDRD) ........................................ 487

14.2.2

A/D Control/Status Register (ADCSR) .......................................................... 488

14.2.3

A/D Control Register (ADCR) ....................................................................... 491

14.3

CPU Interface ................................................................................................................. 492

14.4

Operation ........................................................................................................................ 493

14.4.1

Single Mode (SCAN = 0) ............................................................................... 493

14.4.2

Scan Mode (SCAN = 1).................................................................................. 495

14.4.3

Input Sampling and A/D Conversion Time .................................................... 497

14.4.4

External Trigger Input Timing........................................................................ 498

14.5

Interrupts ........................................................................................................................ 499

14.6

Usage Notes .................................................................................................................... 499

Section 15

RAM ............................................................................................................. 501

15.1

Overview ........................................................................................................................ 501

15.1.1

Block Diagram................................................................................................ 501

15.1.2

15.2

System Control Register (SYSCR)................................................................................. 503

15.3

Operation ........................................................................................................................ 504

Section 16

Clock Pulse Generator............................................................................. 505

16.1

Overview ........................................................................................................................ 505

16.1.1

Block Diagram................................................................................................ 505

16.2

Oscillator Circuit ............................................................................................................ 506

16.2.1

Connecting a Crystal Resonator ..................................................................... 506

16.2.2

External Clock Input....................................................................................... 508

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