H8SLASH3003 datasheet(61/715 Pages) RENESAS

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Table 2-12 Absolute Address Access Ranges

Absolute

Address

1-Mbyte Modes

16-Mbyte Modes

8 bits (@aa:8)

H'FFF00 to H'FFFFF

H'FFFF00 to H'FFFFFF

(1048320 to 1048575)

(16776960 to 16777215)

16 bits (@aa:16)

H'00000 to H'07FFF,

H'000000 to H'007FFF,

H'F8000 to H'FFFFF

H'FF8000 to H'FFFFFF

(0 to 32767, 1015808 to 1048575)

(0 to 32767, 16744448 to 16777215)

24 bits (@aa:24)

H'00000 to H'FFFFF

H'000000 to H'FFFFFF

(0 to 1048575)

(0 to 16777215)

6 Immediate—#xx:8, #xx:16, or #xx:32: The instruction code contains 8-bit (#xx:8), 16-bit

(#xx:16), or 32-bit (#xx:32) immediate data as an operand.

The instruction codes of the ADDS, SUBS, INC, and DEC instructions contain immediate data

implicitly. The instruction codes of some bit manipulation instructions contain 3-bit immediate

data specifying a bit number. The TRAPA instruction code contains 2-bit immediate data

specifying a vector address.

7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and

BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign-

extended to 24 bits and added to the 24-bit PC contents to generate a 24-bit branch address. The

PC value to which the displacement is added is the address of the first byte of the next instruction,

so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768

bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an

even number.

8 Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The

instruction code contains an 8-bit absolute address specifying a memory operand. This memory

operand contains a branch address. The memory operand is accessed by longword access. The

first byte of the memory operand is ignored, generating a 24-bit branch address. See figure 2-10.

The upper bits of the 8-bit absolute address are assumed to be 0 (H'0000), so the address range is

0 to 255 (H'000000 to H'0000FF). Note that the first part of this range is also the exception vector

area. For further details see section 5, Interrupt Controller.

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