H8SLASH3003 datasheet(30/715 Pages) RENESAS

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Table 1-3 Pin Functions (cont)

Pin No.

Type

Symbol

QFP-112

I/O

Name and Function

System control

RES

Input

Reset input: When driven low, this pin resets

the H8/3003

RESO

Output Reset output: Outputs a reset signal to

external devices

STBY

Input

Standby: When driven low, this pin forces

a transition to hardware standby mode

BREQ

Input

Bus request: Used by an external bus master

to request the bus right from the H8/3003

BACK

Output Bus request acknowledge: Indicates that the

bus has been granted to an external bus

master

Interrupts

NMI

Input

Nonmaskable interrupt: Requests a

nonmaskable interrupt

IRQ7 to

18 to 17,

Input

Interrupt request 7 to 0: Maskable interrupt

IRQ0

25 to 24,

request pins

103 to 101

Address bus

A23 to A0

98 to 95,

Output Address bus: Outputs address signals

65 to 54,

52 to 45

Data bus

D15 to D0

43 to 36

Input/

Data bus: Bidirectional data bus

34 to 27

output

Bus control

CS7 to CS0 16 to 13

Output Chip select: Select signals for areas 7 to 0

101 to 104

Output Address strobe: Goes low to indicate valid

address output on the address bus

Output Read: Goes low to indicate reading from the

external address space

HWR

Output High write: Goes low to indicate writing to the

external address space; indicates valid data on

the upper data bus (D15 to D8).

LWR

Output Low write: Goes low to indicate writing to the

external address space; indicates valid data on

the lower data bus (D7 to D0).

WAIT

Input

Wait: Requests insertion of wait states in bus

cycles during access to the external address

space

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