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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8/3003 数据表(PDF) 391 Page - Renesas Technology Corp |
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H8/3003 数据表(HTML) 391 Page - Renesas Technology Corp |
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391 / 715 page  Contention between General Register Write and Input Capture: If an input capture signal occurs in the T3 state of a general register write cycle, input capture takes priority and the write to the general register is not performed. See figure 10-68. Figure 10-68 Contention between General Register Write and Input Capture Note on Waveform Period Setting: When a counter is cleared by compare match, the counter is cleared in the last state at which the TCNT value matches the general register value, at the time when this value would normally be updated to the next count. The actual counter frequency is therefore given by the following formula: f = (f: counter frequency. ø: system clock frequency. N: value set in general register.) ø Address Internal write signal Input capture signal TCNT GR M GR address General register write cycle T1 T2 T3 M ø (N + 1) 373 |
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