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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8/3003 数据表(PDF) 516 Page - Renesas Technology Corp |
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H8/3003 数据表(HTML) 516 Page - Renesas Technology Corp |
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516 / 715 page  Table 14-4 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Symbol Min Typ Max Min Typ Max Synchronization delay tD 10 —17 6 —9 Input sampling time tSPL —80 ——40 — A/D conversion time tCONV 259 — 266 131 — 134 Note: Values in the table are numbers of states. 14.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGE bit is set to 1 in ADCR, external trigger input is enabled at the ADTRG pin. A high-to-low transition at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as if the ADST bit had been set to 1 by software. Figure 14-6 shows the timing. Figure 14-6 External Trigger Input Timing ø ADTRG Internal trigger signal ADST A/D conversion 498 |
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