H8SLASH3003 datasheet(597/715 Pages) RENESAS

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Table A-3 Number of Cycles per Instruction (cont)

Instruction Branch

Stack

Byte Data Word Data Internal

Fetch

Addr. Read Operation Access

Access

Operation

Instruction Mnemonic

RTS

Normal*1

Advanced 2

SHAL

SHAL.B Rd

SHAL.W Rd

SHAL.L ERd

SHAR

SHAR.B Rd

SHAR.W Rd

SHAR.L ERd

SHLL

SHLL.B Rd

SHLL.W Rd

SHLL.L ERd

SHLR

SHLR.B Rd

SHLR.W Rd

SHLR.L ERd

SLEEP

STC

STC CCR, Rd

STC CCR, @ERd

STC CCR, @(d:16, ERd) 3

STC CCR, @(d:24, ERd) 5

STC CCR, @–ERd

STC CCR, @aa:16

STC CCR, @aa:24

SUB

SUB.B Rs, Rd

SUB.W #xx:16, Rd

SUB.W Rs, Rd

SUB.L #xx:32, ERd

SUB.L ERs, ERd

SUBS

SUBS #1/2/4, ERd

SUBX

SUBX #xx:8, Rd

SUBX Rs, Rd

TRAPA

TRAPA #x:2 Normal*1

Advanced 2

XOR

XOR.B #xx:8, Rd

XOR.B Rs, Rd

XOR.W #xx:16, Rd

XOR.W Rs, Rd

XOR.L #xx:32, ERd

XOR.L ERs, ERd

XORC

XORC #xx:8, CCR

Notes: 1. n is the value set in register R4L or R4. The source and destination are accessed n + 1 times each.

2. For the number of states required for data access, refer to the relevant hardware manual.

3. Not available in the H8/3003.

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