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数据搜索系统，热门电子元器件搜索 |
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H8/3003 数据表(PDF) 666 Page - Renesas Technology Corp |
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H8/3003 数据表(HTML) 666 Page - Renesas Technology Corp |
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666 / 715 page  SSR—Serial Status Register H'B4 SCI0 Bit Initial value Read/Write 7 TDRE 1 R/(W) 6 RDRF 0 R/(W) 5 ORER 0 R/(W) 4 FER 0 R/(W) 3 PER 0 R/(W) 0 MPBT 0 R/W 2 TEND 1 R 1 MPB 0 R Transmit end 0 [Clearing conditions] 1 [Setting conditions] Reset or transition to standby mode. TE is cleared to 0 in SCR. TDRE is 1 when last bit of serial character is transmitted. ** * * * Multiprocessor bit transfer Read TDRE when TDRE = 1, then write 0 in TDRE. The DMAC writes data in TDR. Multiprocessor bit Parity error 0 [Clearing conditions] 1 [Setting condition] Parity error: (parity of receive data does not match parity setting of O/ in SMR) Reset or transition to standby mode. Read PER when PER = 1, then write 0 in PER. E Framing error 0 [Clearing conditions] 1 [Setting condition] Framing error (stop bit is 0) Reset or transition to standby mode. Read FER when FER = 1, then write 0 in FER. Overrun error 0 [Clearing conditions] 1 [Setting condition] Overrun error (reception of next serial data ends when RDRF = 1) Reset or transition to standby mode. Read ORER when ORER = 1, then write 0 in ORER. Receive data register full 0 [Clearing conditions] 1 [Setting condition] Serial data is received normally and transferred from RSR to RDR Reset or transition to standby mode. Read RDRF when RDRF = 1, then write 0 in RDRF. The DMAC reads data from RDR. Transmit data register empty 0 [Clearing conditions] 1 [Setting conditions] Reset or transition to standby mode. TE is 0 in SCR Data is transferred from TDR to TSR, enabling new data to be written in TDR. Read TDRE when TDRE = 1, then write 0 in TDRE. The DMAC writes data in TDR. 0 Multiprocessor bit value in receive data is 0 1 Multiprocessor bit value in receive data is 1 0 Multiprocessor bit value in transmit data is 0 1 Multiprocessor bit value in transmit data is 1 Note: Only 0 can be written, to clear the flag. * 648 |
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