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H8/3003 数据表(PDF) 678 Page - Renesas Technology Corp |
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H8/3003 数据表(HTML) 678 Page - Renesas Technology Corp |
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678 / 715 page ![]() ADCSR—A/D Control/Status Register H'E8 A/D Bit Initial value Read/Write 7 ADF 0 R/(W) 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W 3 CKS 0 R/W 0 CH0 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W * Note: Only 0 can be written, to clear flag. * Channel select 2 to 0 CH2 1 Single Mode AN AN AN AN AN AN AN CH1 0 1 0 1 Channel Selection CH0 0 1 0 1 0 1 0 1 0 0 1 2 3 4 5 6 AN 7 Scan Mode AN AN , AN AN to AN AN to AN AN AN , AN AN to AN 0 0 0 0 4 4 4 AN to AN 4 1 5 2 3 6 7 Description Group Selection A/D end flag A/D interrupt enable A/D start Clock select Scan mode 0 [Clearing condition] Read ADF while ADF = 1, then write 0 in ADF 1 [Setting conditions] Single mode: Scan mode: 0 A/D end interrupt request is disabled 1 A/D end interrupt request is enabled 0 A/D conversion is stopped 1 Single mode: Scan mode: 0 Single mode 1 Scan mode 0 Conversion time = 266 states (maximum) 1 Conversion time = 134 states (maximum) A/D conversion ends A/D conversion ends in all selected channels A/D conversion starts; ADST is automatically cleared to 0 when conversion ends A/D conversion starts and continues, cycling among the selected channels, until ADST is cleared to 0 by software, by a reset, or by a transition to standby mode 660 |
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