H8SLASH3003 datasheet(176/715 Pages) RENESAS

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Example 4: Connection to Two 4-Mbit DRAM Chips (16-Mbyte Mode): Figure 7-13 shows

an example of interconnections to two 2

CAS 4-Mbit DRAM chips, and the corresponding address

map. Up to four DRAM chips can be connected to area 3 by decoding upper address bits A19

and A20.

Figure 7-14 shows a setup procedure to be followed by a program for this example. The DRAM

in this example has 9-bit row addresses and 9-bit column addresses. Both chips must be refreshed

simultaneously, so the

RFSH pin must be used.

Figure 7-13 Interconnections and Address Map for Multiple 2

CAS 4-Mbit DRAM Chips

(Example)

H'600000

H'67FFFF

H'680000

H'6FFFFF

H'700000

H'7FFFFF

A to A

RAS

UCAS

LCAS

I/O

to I/O

No. 1

A to A

RAS

UCAS

LCAS

I/O

to I/O

No. 2

A to A

HWR

LWR

RFSH

to D

H8/3003

4-Mbit DRAM with 9-bit

row address, 9-bit column

address, and

16-bit organization

a. Interconnections (example)

b. Address map

No. 1

DRAM area

No. 2

DRAM area

Not used

Area 3 (16-Mbyte mode)

CAS

158

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