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H8/3003 数据表(PDF) 183 Page - Renesas Technology Corp |
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H8/3003 数据表(HTML) 183 Page - Renesas Technology Corp |
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183 / 715 page  7.3.4 Interval Timing To use the refresh controller as an interval timer, clear the PSRAME and DRAME both to 0. After setting RTCOR, select a clock source with bits CKS2 to CKS0 in RTMCSR, and set the CMIE bit to 1. Timing of Setting of Compare Match Flag and Clearing by Compare Match: The CMF flag in RTCSR is set to 1 by a compare match signal output when the RTCOR and RTCNT values match. The compare match signal is generated in the last state in which the values match (when RTCNT is updated from the matching value to a new value). Accordingly, when RTCNT and RTCOR match, the compare match signal is not generated until the next counter clock pulse. Figure 7-19 shows the timing. Figure 7-19 Timing of Setting of CMF Flag Operation in Power-Down State: The interval timer function operates in sleep mode. It does not operate in hardware standby mode. In software standby mode RTCNT and RTMCSR bits 7 and 6 are initialized, but RTMCSR bits 5 to 3 and RTCOR retain their settings prior to the transition to software standby mode. ø RTCNT RTCOR CMF flag N H'00 N Compare match signal 165 |
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