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H8/3003 数据表(PDF) 253 Page - Renesas Technology Corp |
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H8/3003 数据表(HTML) 253 Page - Renesas Technology Corp |
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253 / 715 page  Table 8-14 Address Ranges Specifiable in MAR and IOAR 1-Mbyte Mode 16-Mbyte Mode MAR H'00000 to H'FFFFF H'000000 to H'FFFFFF (0 to 1048575) (0 to 16777215) IOAR H'FFF00 to H'FFFFF H'FFFF00 to H'FFFFFF (1048320 to 1048575) (16776960 to 16777215) MAR bits 23 to 20 are ignored in 1-Mbyte mode. 8.6.8 Bus Cycle when Transfer is Aborted When a transfer is aborted by clearing the DTE bit or suspended by an NMI that clears the DTME bit, if this halts a channel for which the DMAC has a transfer request pending internally, a dead cycle occurs. This dead cycle does not update the halted channel’s address register or counter value. Figure 8-28 shows an example in which an auto-requested transfer in cycle-steal mode on channel 0 is aborted by clearing the DTE bit in channel 0. Figure 8-28 Bus Timing at Abort of DMA Transfer in Cycle-Steal Mode ø Address bus RD GW, LWR CPU cycle DMAC cycle CPU cycle DMAC cycle CPU cycle DTE bit is cleared T1 T2 Td T1 T2 T1 T2 T1 T2 T3 Td Td T1 T2 235 |
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