H8SLASH3028F datasheet(467/923 Pages) RENESAS

467 / 923 page

Rev. 2.00, 09/03, page 437 of 890

Section 12 Watchdog Timer

12.1

Overview

The H8/3028 Group has an on-chip watchdog timer (WDT). The WDT has two selectable

functions: it can operate as a watchdog timer to supervise system operation, or it can operate as an

interval timer. As a watchdog timer, it generates a reset signal for the H8/3028 Group chip if a

system crash allows the timer counter (TCNT) to overflow before being rewritten. In interval

timer operation, an interval timer interrupt is requested at each TCNT overflow.

12.1.1

Features

WDT features are listed below.

• Selection of eight counter clock sources

φ/2, φ /32, φ /64, φ /128, φ /256, φ /512, φ /2048, or φ /4096

• Interval timer option

• Timer counter overflow generates a reset signal or interrupt.

The reset signal is generated in watchdog timer operation. An interval timer interrupt is

generated in interval timer operation.

• It is possible to reset the entire H8/3028 Group using the reset signal generated by the

watchdog timer and simultaneously output the reset signal to an external device.*

The reset signal generated by timer counter overflow during watchdog timer operation resets

the entire H8/3028 Group internally.

At the same time, a reset signal is output by pin

RESO to an external device, making it

possible to reset the entire system.

Note: * In the F-ZTAT mask ROM version, the

RESO pin is for FWE input only. Consequently, it

is not possible to output reset signals to an external device from the F-ZTAT version.

H8/3028F 数据表(PDF) 467 Page - Renesas Technology Corp