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H8/3028F 数据表(PDF) 536 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 536 Page - Renesas Technology Corp |
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536 / 923 page ![]() Rev. 2.00, 09/03, page 506 of 890 13.4 SCI Interrupts The SCI has four interrupt request sources: the transmit-end interrupt (TEI), receive-error interrupt (ERI), receive-data-full interrupt (RXI), and transmit-data-empty interrupt (TXI). Table 13.12 lists the interrupt sources and indicates their priority. These interrupts can be enabled or disabled by the TIE, RIE, and TEIE bits in SCR. Each interrupt request is sent separately to the interrupt controller. A TXI interrupt is requested when the TDRE flag is set to 1 in SSR. A TEI interrupt is requested when the TEND flag is set to 1 in SSR. A TXI interrupt request can activate the DMAC to transfer data. Data transfer by the DMAC automatically clears the TDRE flag to 0. A TEI interrupt request cannot activate the DMAC. An RXI interrupt is requested when the RDRF flag is set to 1 in SSR. An ERI interrupt is requested when the ORER, PER, or FER flag is set to 1 in SSR. An RXI interrupt can activate the DMAC to transfer data. Data transfer by the DMAC automatically clears the RDRF flag to 0. An ERI interrupt request cannot activate the DMAC. The DMAC can be activated by interrupts from SCI channel 0. Table 13.12 SCI Interrupt Sources Interrupt Source Description Priority ERI Receive error (ORER, FER, or PER) High RXI Receive data register full (RDRF) TXI Transmit data register empty (TDRE) TEI Transmit end (TEND) Low 13.5 Usage Notes 13.5.1 Notes on Use of SCI Note the following points when using the SCI. TDR Write and TDRE Flag: The TDRE flag in SSR is a status flag indicating the loading of transmit data from TDR to TSR. The SCI sets the TDRE flag to 1 when it transfers data from TDR to TSR. Data can be written into TDR regardless of the state of the TDRE flag. If new data is written in TDR when the TDRE flag is 0, the old data stored in TDR will be lost because this data has not yet been transferred to TSR. Before writing transmit data in TDR, be sure to check that the TDRE flag is set to 1. |
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