H8SLASH3028F datasheet(537/923 Pages) RENESAS

537 / 923 page

Rev. 2.00, 09/03, page 507 of 890

Simultaneous Multiple Receive Errors: Table 13.13 shows the state of the SSR status flags

when multiple receive errors occur simultaneously. When an overrun error occurs the RSR

contents are not transferred to RDR, so receive data is lost.

Table 13.13 SSR Status Flags and Transfer of Receive Data

SSR Status Flags

RDRF

ORER

FER

PER

Receive Data

Transfer

RSR

→

→ RDR

Receive Errors

Overrun error

Framing error

Parity error

Overrun error + framing error

Overrun error + parity error

Framing error + parity error

Overrun error + framing error + parity

error

Notes:

: Receive data is transferred from RSR to RDR.

× : Receive data is not transferred from RSR to RDR.

Break Detection and Processing: Break signals can be detected by reading the RxD pin directly

when a framing error (FER) is detected. In the break state the input from the RxD pin consists of

all 0s, so the FER flag is set and the parity error flag (PER) may also be set. In the break state the

SCI receiver continues to operate, so if the FER flag is cleared to 0 it will be set to 1 again.

Sending a Break Signal: The input/output condition and level of the TxD pin are determined by

DR and DDR bits. This feature can be used to send a break signal.

After the serial transmitter is initialized, the DR value substitutes for the mark state until the TE

bit is set to 1 (the TxD pin function is not selected until the TE bit is set to 1). The DDR and DR

bits should therefore be set to 1 beforehand.

To send a break signal during serial transmission, clear the DR bit to 0 , then clear the TE bit to 0.

When the TE bit is cleared to 0 the transmitter is initialized, regardless of its current state, so the

TxD pin becomes an input/output outputting the value 0.

Receive Error Flags and Transmitter Operation (Synchronous Mode Only): When a receive

error flag (ORER, PER, or FER) is set to 1 the SCI will not start transmitting, even if the TDRE

flag is cleared to 0. Be sure to clear the receive error flags to 0 when starting to transmit. Note

that clearing the RE bit to 0 does not clear the receive error flags to 0.

Receive Data Sampling Timing in Asynchronous Mode and Receive Margin: In asynchronous

mode the SCI operates on a base clock with 16 times the bit rate frequency. In receiving, the SCI

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