H8SLASH3028F datasheet(538/923 Pages) RENESAS

部件名	H8/3028F

功能描述	Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

PDF	923 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

标志

538 / 923 page

Rev. 2.00, 09/03, page 508 of 890

synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive

data is latched at the rising edge of the eighth base clock pulse. See figure 13.21.

15 0

Internal base clock

8 clocks

Receive data

(RxD)

Synchronization

sampling timing

Data sampling

timing

15 0

Start bit

16 clocks

Figure 13.21 Receive Data Sampling Timing in Asynchronous Mode

The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).

M =

(0.5 –

D – 0.5

) – (L – 0.5) F –

(1 + F)

× 100%

. . . . . . . . (1)

M: Receive margin (%)

N: Ratio of clock frequency to bit rate (N = 16)

D: Clock duty cycle (L = 0 to 1.0)

Frame length (L = 9 to 12)

Absolute deviation of clock frequency

From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2).

M =

× 16

)

× 100%

(0.5 –

D = 0.5, F = 0

= 46.875%

. . . . . . . . (2)

This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.

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