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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8/3028F 数据表(PDF) 699 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 699 Page - Renesas Technology Corp |
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699 / 923 page  Rev. 2.00, 09/03, page 669 of 890 Condition f = 2 M to 25 MHz Module Item Symbol Min Max Unit Test Conditions SCI Input clock cycle Asyn- chronous tScyc 4— tcyc Figure 21.23 Syn- chronous 6— tcyc Input clock rise time tSCKr —1.5 tcyc Input clock fall time tSCKf —1.5 tcyc Input clock pulse width tSCKW 0.4 0.6 tScyc Transmit data delay time tTXD — 100 ns Figure 21.24 Receive data setup time (synchronous) tRXS 100 — ns Clock input tRXH 100 — ns Receive data hold time (syn- chronous) Clock output 0 — ns DMAC TEND delay time 1 tTED1 —50 ns TEND delay time 2 tTED2 —50 ns Figure 21.25, figure 21.26 DREQ setup time tDRQS 25 — ns Figure 21.27 DREQ hold time tDRQH 10 — ns CRH RL H8/3028F-ZTAT output pin C = 90 pF: ports 1 to 5, 66 to 60, 8, A19 to A0, D15 to D8, C = 30 pF: ports 9, A, B RL = 2.4 kΩ RH = 12 kΩ Input/output timing measurement levels • Low: 0.8 V • High: 2.0 V φ Figure 21.6 Output Load Circuit |
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