H8SLASH3028F datasheet(139/923 Pages) RENESAS

139 / 923 page

Rev. 2.00, 09/03, page 109 of 890

6.1.2

Block Diagram

Figure 6.1 shows a block diagram of the bus controller.

Internal address bus

ABWCR

ASTCR

BCR

CSCR

ADRCR

Area

decoder

Chip select

control signals

CS0 to CS7

Bus control

circuit

WCRH

WCRL

BRCR

DRAM control

Legend

DRAM interface

Wait state

controller

WAIT

BACK

BREQ

CPU bus request signal

DMAC bus request signal

DRAM interface bus request signal

CPU bus acknowledge signal

DMAC bus acknowledge signal

DRAM interface bus acknowledge signal

Bus arbiter

Bus mode control signal

Internal signals

Bus size control signal

Access state control signal

Wait request signal

: Bus width control register

: Access state control register

: DRAM control register A

: DRAM control register B

: Wait control register H

: Wait control register L

: Bus release control register

: Chip select control register

: Refresh timer control/status register

: Refresh timer counter

: Refresh time constant register

ASTCR

DRCRA

DRCRB

WCRH

WCRL

BRCR

CSCR

RTMCSR

RTCNT

RTCOR

ADRCR

: Address control register

ABWCR

DRCRA

DRCRB

RTMCSR

RTCNT

RTCOR

BCR

: Bus control register

Figure 6.1 Block Diagram of Bus Controller

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