H8SLASH3028F datasheet(142/923 Pages) RENESAS

142 / 923 page

Rev. 2.00, 09/03, page 112 of 890

6.2

6.2.1

Bus Width Control Register (ABWCR)

ABWCR is an 8-bit readable/writable register that selects 8-bit or 16-bit access for each area.

ABW7

R/W

ABW6

R/W

ABW5

R/W

ABW4

R/W

ABW3

R/W

ABW2

R/W

ABW1

R/W

ABW0

R/W

Bit

Modes

1, 3, 5, 6,

and 7

Initial value

Read/Write

Initial value

Read/Write

Modes

2 and 4

When ABWCR contains H'FF (selecting 8-bit access for all areas), the chip operates in 8-bit bus

mode: the upper data bus (D15 to D8) is valid, and port 4 is an input/output port. When at least one

bit is cleared to 0 in ABWCR, the chip operates in 16-bit bus mode with a 16-bit data bus (D15 to

D0). In modes 1, 3, 5, 6, and 7, ABWCR is initialized to H'FF by a reset and in hardware standby

mode. In modes 2 and 4, ABWCR is initialized to H'00 by a reset and in hardware standby mode.

It is not initialized in software standby mode.

Bits 7 to 0—Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select 8-bit access

or 16-bit access for the corresponding areas.

Bits 7 to 0

ABW7 to ABW0

Description

Areas 7 to 0 are 16-bit access areas

Areas 7 to 0 are 8-bit access areas

ABWCR specifies the data bus width of external memory areas. The data bus width of on-chip

memory and registers is fixed, and does not depend on ABWCR settings. These settings are

therefore meaningless in the single-chip modes (modes 6 and 7).

H8/3028F 数据表(PDF) 142 Page - Renesas Technology Corp

H8/3028F 数据表(HTML) 142 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载