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H8/3028F 数据表(PDF) 141 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 141 Page - Renesas Technology Corp |
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141 / 923 page ![]() Rev. 2.00, 09/03, page 111 of 890 6.1.4 Register Configuration Table 6.2 summarizes the bus controller's registers. Table 6.2 Bus Controller Registers Address* 1 Name Abbreviation R/W Initial Value H'EE020 Bus width control register ABWCR R/W H'FF* 2 H'EE021 Access state control register ASTCR R/W H'FF H'EE022 Wait control register H WCRH R/W H'FF H'EE023 Wait control register L WCRL R/W H'FF H'EE013 Bus release control register BRCR R/W H'FE* 3 H'EE01F Chip select control register CSCR R/W H'0F H'EE01E Address control register ADRCR R/W H'FF H'EE024 Bus control register BCR R/W H'C6 H'EE026 DRAM control register A DRCRA R/W H'10 H'EE027 DRAM control register B DRCRB R/W H'08 H'EE028 Refresh timer control/status register RTMCSR R(W)* 4 H'07 H'EE029 Refresh timer counter RTCNT R/W H'00 H'EE02A Refresh time constant register RTCOR R/W H'FF Notes: 1. Lower 20 bits of the address in advanced mode. 2. In modes 2 and 4, the initial value is H'00. 3. In modes 3 and 4, the initial value is H'EE. 4. For Bit 7, only 0 can be written to clear the flag. |
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