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H8/3028F 数据表(PDF) 140 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 140 Page - Renesas Technology Corp |
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140 / 923 page ![]() Rev. 2.00, 09/03, page 110 of 890 6.1.3 Pin Configuration Table 6.1 summarizes the input/output pins of the bus controller. Table 6.1 Bus Controller Pins Name Abbreviation I/O Function Chip select 0 to 7 CS0 to CS7 Output Strobe signals selecting areas 0 to 7 Address strobe AS Output Strobe signal indicating valid address output on the address bus Read RD Output Strobe signal indicating reading from the external address space High write HWR Output Strobe signal indicating writing to the external address space, with valid data on the upper data bus (D15 to D8) Low write LWR Output Strobe signal indicating writing to the external address space, with valid data on the lower data bus (D7 to D0) Wait WAIT Input Wait request signal for access to external three-state access areas Bus request BREQ Input Request signal for releasing the bus to an external device Bus acknowledge BACK Output Acknowledge signal indicating release of the bus to an external device |
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