H8SLASH3028F datasheet(149/923 Pages) RENESAS

149 / 923 page

Rev. 2.00, 09/03, page 119 of 890

Bit 7—Idle Cycle Insertion 1 (ICIS1): Selects whether one idle cycle state is to be inserted

between bus cycles in case of consecutive external read cycles for different areas.

Bit 7

ICIS1

Description

No idle cycle inserted in case of consecutive external read cycles for different

areas

Idle cycle inserted in case of consecutive external read cycles for different

areas

(Initial value)

Bit 6—Idle Cycle Insertion 0 (ICIS0): Selects whether one idle cycle state is to be inserted

between bus cycles in case of consecutive external read and write cycles.

Bit 6

ICIS0

Description

No idle cycle inserted in case of consecutive external read and write cycles

Idle cycle inserted in case of consecutive external read and write cycles

(Initial value)

Bit 5—Burst ROM Enable (BROME): Selects whether area 0 is a burst ROM interface area.

Bit 5

BROME

Description

Area 0 is a basic bus interface area

(Initial value)

Area 0 is a burst ROM interface area

Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycle states for the burst

ROM interface.

Bit 4

BRSTS1

Description

Burst access cycle comprises 2 states

(Initial value)

Burst access cycle comprises 3 states

H8/3028F 数据表(PDF) 149 Page - Renesas Technology Corp