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H8/3028F 数据表(PDF) 152 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 152 Page - Renesas Technology Corp |
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152 / 923 page  Rev. 2.00, 09/03, page 122 of 890 6.2.7 DRAM Control Register A (DRCRA) BE RDM SRFMD RFSHE 0 Initial value 0010000 Read/Write R/W R/W R/W R/W R/W R/W R/W — 76543210 DRAS2 DRAS1 DRAS0 — Bit DRCRA is an 8-bit readable/writable register that selects the areas that have a DRAM interface function, and the access mode, and enables or disables self-refreshing and refresh pin output. DRCRA is initialized to H'10 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 5—DRAM Area Select (DRAS2 to DRAS0): These bits select which of areas 2 to 5 are to function as DRAM interface areas (DRAM space) in expanded mode, and at the same time select the RAS output pin corresponding to each DRAM space. Description Bit 7 DRAS2 Bit 6 DRAS1 Bit 5 DRAS0 Area 5 Area 4 Area 3 Area 2 0 0 0 Normal Normal Normal Normal 1 Normal Normal Normal DRAM space ( CS2) 1 0 Normal Normal DRAM space ( CS3) DRAM space ( CS2) 1 Normal Normal DRAM space ( CS2)* DRAM space ( CS2)* 1 0 0 Normal DRAM space ( CS4) DRAM space ( CS3) DRAM space ( CS2) 1 DRAM space ( CS5) DRAM space ( CS4) DRAM space ( CS3) DRAM space ( CS2) 1 0 DRAM space ( CS4)* DRAM space ( CS4)* DRAM space ( CS2)* DRAM space ( CS2)* 1 DRAM space ( CS2)* DRAM space ( CS2)* DRAM space ( CS2)* DRAM space ( CS2)* Note: * A single CSn pin serves as a common RAS output pin for a number of areas. Unused CSn pins can be used as input/output ports. When any of bits DRAS2 to DRAS0 is set to 1 in expanded mode, it is not possible to write to DRCRB, RTMCSR, RTCNT, or RTCOR. However, 0 can be written to the CMF flag in RTMCSR to clear the flag. |
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