H8SLASH3028F datasheet(154/923 Pages) RENESAS

154 / 923 page

Rev. 2.00, 09/03, page 124 of 890

Bit 0—Refresh Pin Enable (RFSHE): Enables or disables

RFSH pin refresh signal output. If

areas 2 to 5 are not designated as DRAM space, this bit should not be set to 1.

Bit 0

RFSHE

Description

RFSH pin refresh signal output disabled

(Initial value)

(

RFSH pin can be used as input/output port)

RFSH pin refresh signal output enabled

6.2.8

DRAM Control Register B (DRCRB)

—

TPC

RCW

RLW

Initial value

01000

Read/Write

—

R/W

76543210

MXC1

MXC0

CSEL

RCYCE

Bit

DRCRB is an 8-bit readable/writable register that selects the number of address multiplex column

address bits for the DRAM interface, the column address strobe output pin, enabling or disabling

of refresh cycle insertion, the number of precharge cycles, enabling or disabling of wait state

insertion between

RAS and CAS, and enabling or disabling of wait state insertion in refresh

cycles.

DRCRB is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

The settings in this register are invalid when bits DRAS2 to DRAS0 in DRCRA are all 0.

Bits 7 and 6—Multiplex Control 1 and 0 (MXC1, MXC0): These bits select the row

address/column address multiplexing method used on the DRAM interface. In burst operation, the

row address used for comparison is determined by the setting of these bits and the bus width of the

relevant area set in ABWCR.

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