H8SLASH3028F datasheet(151/923 Pages) RENESAS

151 / 923 page

Rev. 2.00, 09/03, page 121 of 890

Bit 0—WAIT Pin Enable (WAITE): Enables or disables wait insertion by means of the

WAIT

pin.

Bit 0

WAITE

Description

WAIT pin wait input is disabled, and the WAIT pin can be used as an

input/output port

(Initial value)

WAIT pin wait input is enabled

6.2.6

Chip Select Control Register (CSCR)

CSCR is an 8-bit readable/writable register that enables or disables output of chip select signals

(

7 to CS4).

If output of a chip select signal is enabled by a setting in this register, the corresponding pin

functions as a chip select signal (

7 to CS4) output regardless of any other settings. CSCR

cannot be modified in single-chip mode.

————

Initial value

0001111

Read/Write

———

—

R/W

76543210

Reserved bits

CS7E

CS6E

CS5E

CS4E

Chip select 7 to 4 enable

These bits enable or disable

chip select signal output

Bit

CSCR is initialized to H'0F by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bits 7 to 4—Chip Select 7 to 4 Enable (CS7E to CS4E): These bits enable or disable output of

the corresponding chip select signal.

Bit n

CSnE

Description

Output of chip select signal

CSn is disabled

(Initial value)

Output of chip select signal

CSn is enabled

Note: n = 7 to 4

Bits 3 to 0—Reserved: These bits cannot be modified and are always read as 1.

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