H8SLASH3028F datasheet(157/923 Pages) RENESAS

157 / 923 page

Rev. 2.00, 09/03, page 127 of 890

initialized to 0 by a reset and in hardware standby mode; they are not initialized in software

standby mode.

Bit 7—Compare Match Flag (CMF): Status flag that indicates a match between the values of

RTCNT and RTCOR.

Bit 7

CMF

Description

[Clearing conditions]

When the chip is reset and in standby mode

Read CMF when CMF = 1, then write 0 in CMF

(Initial value)

[Setting condition]

When RTCNT = RTCOR

Bit 6—Compare Match Interrupt Enable (CMIE): Enables or disables the CMI interrupt

requested when the CMF flag is set to 1 in RTMCSR. The CMIE bit is always cleared to 0 when

any of areas 2 to 5 is designated as DRAM space.

Bit 6

CMIE

Description

The CMI interrupt requested by CMF is disabled

(Initial value)

The CMI interrupt requested by CMF is enabled

Bits 5 to 3—Refresh Counter Clock Select (CKS2 to CKS0): These bits select the clock to be

input to RTCNT from among 7 clocks obtained by dividing the system clock (

φ). When the input

clock is selected with bits CKS2 to CKS0, RTCNT begins counting up.

Bit 5

CKS2

Bit 4

CKS1

Bit 3

CKS0

Description

Count operation halted

(Initial value)

φ/2 used as counter clock

φ/8 used as counter clock

φ/32 used as counter clock

100

φ/128 used as counter clock

φ/512 used as counter clock

φ/2048 used as counter clock

φ/4096 used as counter clock

Bits 2 to 0—Reserved: These bits cannot be modified and are always read as 1.

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