H8SLASH3028F datasheet(156/923 Pages) RENESAS

156 / 923 page

Rev. 2.00, 09/03, page 126 of 890

Bit 3—Reserved: This bit cannot be modified and is always read as 1.

Bit 2—TP Cycle Control (TPC): Selects whether a 1-state or two-state precharge cycle (TP) is to

be used for DRAM read/write cycles and CAS-before-RAS refresh cycles.

The setting of this bit does not affect the self-refresh function.

Bit 2

TPC

Description

1-state precharge cycle inserted

(Initial value)

2-state precharge cycle inserted

Bit 1—

RAS

RAS-CAS

CAS

CAS Wait (RCW): Controls wait state (Trw) insertion between T

r and Tc1 in DRAM

read/write cycles. The setting of this bit does not affect refresh cycles.

Bit 1

RCW

Description

Wait state (Trw) insertion disabled

(Initial value)

One wait state (Trw) inserted

Bit 0—Refresh Cycle Wait Control (RLW): Controls wait state (TRW) insertion for CAS-before-

RAS refresh cycles. The setting of this bit does not affect DRAM read/write cycles.

Bit 0

RLW

Description

Wait state (TRW) insertion disabled

(Initial value)

One wait state (TRW) inserted

6.2.9

Refresh Timer Control/Status Register (RTMCSR)

CKS0

———

Initial value

0000111

Read/Write

R/W

——

—

R(W)

R/W

76543210

CMF

CMIE

CKS2

CKS1

Bit

Note: * Only 0 can be written to clear the flag.

RTMCSR is an 8-bit readable/writable register that selects the refresh timer counter clock. When

the refresh timer is used as an interval timer, RTMCSR also enables or disables interrupt requests.

Bits 7 and 6 of RTMCSR are initialized to 0 by a reset and in the standby modes. Bits 5 to 3 are

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