AT89C5122D-RDRUM datasheet(65/208 Pages) ATMEL

65 / 208 page

AT83R5122, AT8xC5122/23

4202F–SCR–07/2008

IEC7816-3 says this procedure is mandatory in ATR for card supporting T=0 while EMV

says this procedure is mandatory for T=0 but does not apply for ATR.

Functional Description

The architecture of the Smart Card Interface Block can be detailed as follows:

Barrel Shifter

The Barrel Shifter performs the translation between 1 bit serial data and 8 bits parallel

data

The barrel function is useful for character repetition since the character is still present in

the shifter at the end of the character transmission.

This shifter is able to shift the data in both directions and to invert the input or output

value in order to manage both direct and inverse ISO7816-3 convention.

Coupled with the barrel shifter is a parity checker and generator.

There are 2 registers connected to this barrel shifter, one for the transmission and one

for the reception. They act as buffers to relieve the CPU of timing constraints.

SCART FSM

(Smart Card Asynchronous Receiver Transmitter Finite State Machine)

This is the core of the block. Its purpose is to control the barrel shifter. To sequence cor-

rectly the barrel shifter for a reception or a transmission, it uses the signals issued by the

different counters. One of the most important counters is the guard time counter that

gives time slots corresponding to the character frame.

The SCART FSM is enabled only in UART mode.

The transition from the receipt mode to the transmit mode is done automatically. Priority

is given to the transmission. Transmission refers to Terminal transmission to the ICC.

Reception refers to reception by the Terminal from the ICC.

ETU Counter

The ETU (Elementary Timing Unit) counter controls the working frequency of the barrel

shifter, in fact it generates the enable signal of the barrel shifter. It receives the Card

Clock, and generates the ETU clock. The Card Clock frequency is called “f” below. The

ETU counter is 11 bit wide.

A special compensation mode can be activated. It accomodates situations where the

ETU is not an integer number of Card Clock (CK_ISO). The compensation mode is con-

trolled by the COMP bit in SCETU1 register bit position 7. With COMP=1 the ETU of

every character even bits is reduced by 1 Card Clock period. As a result, the average

ETU is : ETU_average = (ETU - 0.5). One should bear in mind that the ETU counter

should be programmed to deliver a faster ETU which will be reduced by the COMP

mechanism, not the other way around. This allows to reach the required precision of the

character duration specified by the ISO7816-3 standard.

Example1 : F=372, D=32 => ETU= F/D = 11.625 clock cycles.

We select ETU[10-0] = 12 , COMP=1. ETUaverage= 12 - (0.5*COMP) = 11.5

The result will be a full character duration (10 bit) = (10 - 0.107)*ETU. The EMV specifi-

cation is (10 +/- 0.2)*ETU

Guard Time Counter

The minimum time between the leading edge of the start bit of 2 consecutive characters

transmitted by the Terminal is controlled by the Guard Time counter, as described in

Figure 32.

AT89C5122D-RDRUM 数据表(PDF) 65 Page - ATMEL Corporation

AT89C5122D-RDRUM 数据表(HTML) 65 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载