AT89C5122D-RDRUM datasheet(50/208 Pages) ATMEL

50 / 208 page

AT83R5122, AT8xC5122/23

4202F–SCR–07/2008

Reset Value = XXXX XXX0b

Reset Value = 0000 0000b

Table 27.

Clock Configuration Register 1 - CKCON1 (S:AFh) only for AT8xC5122

765

43210

----

---

SPIX2

Bit Number

Bit Mnemonic Description

7 - 4

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

0SPIX2

SPI clock

This control bit is validated when the CPU clock X2 is set. When X2 is low,

this bit has no effect.

Cleared to bypass the 1/2 prescaler.

Set to select the 1/2 output for this peripheral.

Table 28.

PLL Control Register - PLLCON (S:A3h)

765

43210

EXT48

PLLEN

PLOCK

Bit Number

Bit Mnemonic Description

7 - 3

Reserved

The value read from these bits is always 0. Do not set this bits.

2EXT48

External 48 MHz Enable Bit

Set this bit to select XTAL1 as USB clock.

Clear this bit to select PLL as USB clock.

SCIB clock is controlled by EXT48 bit and XTSCS bit.

1PLLEN

PLL Enable bit

Set to enable the PLL.

Clear to disable the PLL.

0PLOCK

PLL Lock Indicator

Set by hardware when PLL is locked

Clear by hardware when PLL is unlocked

Table 29.

PLL Divider Register - PLLDIV (S:A4h)

765

43210

Bit Number

Bit Mnemonic Description

7 - 4

R3:0

PLL R Divider Bits

3 - 0

N3:0

PLL N Divider Bits

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