AT89C5122D-RDRUM datasheet(100/208 Pages) ATMEL

100 / 208 page

100

AT83R5122, AT8xC5122/23

4202F–SCR–07/2008

Read/Write Data FIFO

Read Data FIFO

The read access for each OUT endpoint is performed using the UEPDATX register.

After a new valid packet has been received on an Endpoint, the data are stored into the

FIFO and the byte counter of the endpoint is updated (UBYCTX register). The firmware

has to store the endpoint byte counter before any access to the endpoint FIFO. The byte

counter is not updated when reading the FIFO.

To read data from an endpoint, select the correct endpoint number in UEPNUM and

read the UEPDATX register. This action automatically decreases the corresponding

address vector, and the next data is then available in the UEPDATX register.

Write Data FIFO

The write access for each IN endpoint is performed using the UEPDATX register.

To write a byte into an IN endpoint FIFO, select the correct endpoint number in UEP-

NUM and write into the UEPDATX register. The corresponding address vector is

automatically increased, and another write can be carried out.

Warning 1: The byte counter is not updated.

Warning 2: Do not write more bytes than supported by the corresponding endpoint.

Figure 53.

Endpoint FIFO Configuration

Endpoint 0 - bank 0

Endpoint 1 - bank 0

Endpoint 2 - bank 0

Endpoint 3 - bank 0

Endpoint 4 - bank 0

Endpoint 5 - bank 0

Endpoint 6 - bank 0

Endpoint 6 - bank 1

8 Bytes

32 Bytes

8 Bytes

64 Bytes

2 x 64 Bytes

00H

20H

28H

30H

38H

78H

B8H

F8H

138H

64 Bytes

AT89C5122D-RDRUM 数据表(PDF) 100 Page - ATMEL Corporation

AT89C5122D-RDRUM 数据表(HTML) 100 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载