AT89C5122D-RDRUM datasheet(102/208 Pages) ATMEL

102 / 208 page

102

AT83R5122, AT8xC5122/23

4202F–SCR–07/2008

Bulk/Interrupt OUT

Transactions in Ping-Pong

Mode (Endpoints 6)

Figure 55.

Bulk / Interrupt OUT Transactions in Ping-Pong Mode

An endpoint should be first enabled and configured before being able to receive Bulk or

Interrupt packets.

When a valid OUT packet is received on the endpoint bank 0, the RXOUTB0 bit is set by

the USB controller. This triggers an interrupt if enabled. The firmware has to select the

corresponding endpoint, store the number of data bytes by reading the UBYCTX regis-

ter. If the received packet is a ZLP (Zero Length Packet), the UBYCTX register value is

equal to 0 and no data has to be read.

When all the endpoint FIFO bytes have been read, the firmware should clear the

RXOUB0 bit to allow the USB controller to accept the next OUT packet on the endpoint

bank 0. This action switches the endpoint bank 0 and 1. Until the RXOUTB0 bit has

been cleared by the firmware, the USB controller will answer a NAK handshake for each

OUT requests on the bank 0 endpoint FIFO.

When a new valid OUT packet is received on the endpoint bank 1, the RXOUTB1 bit is

set by the USB controller. This triggers an interrupt if enabled. The firmware empties the

bank 1 endpoint FIFO before clearing the RXOUTB1 bit. Until the RXOUTB1 bit has

been cleared by the firmware, the USB controller will answer a NAK handshake for each

OUT requests on the bank 1 endpoint FIFO.

The RXOUTB0 and RXOUTB1 bits are alternatively set by the USB controller at each

new valid packet receipt.

The firmware has to clear one of these two bits after having read all the data FIFO to

allow a new valid packet to be stored in the corresponding bank.

A NAK handshake is sent by the USB controller only if the banks 0 and 1 has not been

released by the firmware.

OUT

DATA0 (n bytes)

ACK

HOST

UFI

C51

Endpoint FIFO bank 0 - read byte 1

RXOUTB0

Endpoint FIFO bank 0 - read byte 2

Endpoint FIFO bank 0 - read byte n

Clear RXOUTB0

OUT

DATA1 (m bytes)

ACK

RXOUTB1

Endpoint FIFO bank 1 - read byte 1

Endpoint FIFO bank 1 - read byte 2

Endpoint FIFO bank 1 - read byte m

Clear RXOUTB1

OUT

DATA0 (p bytes)

ACK

RXOUTB0

Endpoint FIFO bank 0 - read byte 1

Endpoint FIFO bank 0 - read byte 2

Endpoint FIFO bank 0 - read byte p

Clear RXOUTB0

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