AT89C5122D-RDRUM datasheet(73/208 Pages) ATMEL

73 / 208 page

AT83R5122, AT8xC5122/23

4202F–SCR–07/2008

Transmit / Receive Buffer

The contents of the SCIBUF Transmit / Receive Buffer is transferred or received into /

from the Shift Register. The Shift Register is not accessible by microcontroller. Its role is

to prepare the byte to be copied on the I/O pin for a transmission or in the SCIBUF

buffer after a reception.

During a character transmission process, as soon as the contents of the SCIBUF buffer

is transferred to the shift register, the SCTBE bit is set in SCISR register to indicate that

the SCIBUF buffer is empty and ready to accept a new byte. This mechanism avoids to

wait for the complete transmission of the previous byte before writing a new byte in the

buffer and enables to speed up the transmission.

–

If the Character repetition mode is not selected (bit CREP=0 in SCICR), as

soon as the contents of the Shift Register is transferred to I/O pin, the SCTC

bit is set in SCISR register to indicate that the byte has been transmitted.

–

If the Character repetition mode is selected (bit CREP=1 in SCICR) The

TERMINAL will be able to repeat characters as requested by the ICC (See

the Parity Error in T=0 protocol description in the definition paragraph

above). The SCTC bit in SCISR register will be set after a successful

transmission (no retry or no further retry requested by the ICC). If the

number of retries is exhausted (up to 4 retries depending on CREPSEL bit in

SCSR) and the last retry is still unsuccessful, the SCTC bit in SCISR will not

be set and the SCPE bit in SCISR register will be set instead.

During a character reception process, the contents of the Shift Register is transferred in

the SCIBUF buffer.

–

If the Character repetition mode is not selected (bit CREP=0 in SCICR), as

soon as the contents of the Shift Register is transferred to the SCIBUF the

SCRC bit is set in SCISR register to indicate that the byte has been

received, and the SCIBUF contains a valid character ready to be red by the

microcontroller.

–

If the Character repetition mode is selected (bit CREP=1 in SCICR) The

TERMINAL will be able to request repetition if the received character exhibit

a parity error. Up to 4 retries can be requested depending on CREPSEL bit

in SCSR. The SCRC bit will be set in SCISR register after a successful

reception, first reception or after retry(ies). If the number of retries is

exhausted (up to 4 retries depending on CREPSEL bit in SCSR) and the last

retry is still unsuccessful, the SCRC bit and the SCPE bit in SCISR register

will be set. It will be possible to read the erroneous character.

Warning

: the SCTBI, SCTI SCRI and SCPI bits have the same function as SCTBE,

SCTC, SCRC and SCPE bits. The first ones are able to generate interruptions if the

interruptions are enabled in SCIER register while the second ones are only status bits to

be used in pulling mode. If the interruption mode is not used, the status bits must be

used. The SCTBI, SCTI and SCRI bits do not contain valid information while their

respective interrupt enable bits ESCTBI, EXCTI, ESCRI are cleared.

AT89C5122D-RDRUM 数据表(PDF) 73 Page - ATMEL Corporation

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