AT89C5122D-RDRUM datasheet(40/208 Pages) ATMEL

40 / 208 page

AT83R5122, AT8xC5122/23

4202F–SCR–07/2008

Phase Lock Loop (PLL)

PLL Description

The AT83R5122, AT8xC5122/23’s PLL is used to generate internal high frequency

clock synchronized with an external low-frequency. Figure 16 shows the internal struc-

ture of the PLL.

The PFLD block is the Phase Frequency Comparator and Lock Detector. This block

makes the comparison between the reference clock coming from the N divider and the

reverse clock coming from the R divider and generates some pulses on the Up or Down

signal depending on the edge position of the reverse clock. The PLLEN bit in PLLCON

in PLLCON register is set.

The CHP block is the Charge Pump that generates the voltage reference for the VCO by

injecting or extracting charges from the external filter connected on PLLF pin (see

Figure 17). Value of the filter components are detailed in the Section “DC

Characteristics”.

The VCO block is the Voltage Controlled Oscillator controlled by the voltage VREF pro-

duced by the charge pump. It generates a square wave signal: the PLL clock. The

CK_PLL frequency is defined by the follwing formula:

FCK_PLL = FCK_XTAL1 * (R+1) / (N+1)

Figure 16.

PLL Block Diagram and Symbol

Figure 17.

PLL Filter Value

PLL Programming

The PLL must be programmed to work at 96 MHz frequency by means of PLLCON and

PLLDIV registers. As soon as the PLL is enabled, the firmware must wait for the lock bit

status to ensure that the PLL is ready.

PLLEN

PLLCON.1

N3:0

N Divider

R divider

VCO

CK_PLL

CK_XTAL1

PFLD

PLOCK

PLLCON.0

PLLF

CHP

VREF

Down

R3:0

VSS

PLLF

VSS

1,8 K

150 pF

33 pF

AT89C5122D-RDRUM 数据表(PDF) 40 Page - ATMEL Corporation

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