AT89C5122D-RDRUM datasheet(94/208 Pages) ATMEL

94 / 208 page

AT83R5122, AT8xC5122/23

4202F–SCR–07/2008

The only possible value for the wMaxPacketSize in the DFU configuration is 32 bytes,

which is the size of the FIFO implemented for endpoint 0.

Description

The USB device controller provides the hardware that the AT8xC5122D and the

AT83C5123 need to interface a USB link to a data flow stored in a double port memory

(DPRAM).

The USB controller requires a 48 MHz reference clock, which is the output of the

AT8xC5122D/23 PLL (see Section "Phase Lock Loop (PLL)", page 40) divided by a

clock prescaler. This clock is used to generate a 12 MHz full speed bit clock from the

received USB differential data and to transmit data according to full speed USB device

tolerance. Clock recovery is done by a Digital Phase Locked Loop (DPLL) block, which

is compliant with the jitter specification of the USB bus.

The Interface Engine (SIE) block performs NRZI encoding and decoding, bit stuffing,

CRC generation and checking, and the serial-parallel data conversion. The Universal

Function Interface (UFI) performs the interface between the data flow and the Dual Port

Ram

Figure 48.

USB Device Controller Block Diagram

Serial Interface Engine (SIE)

The SIE performs the following functions:

•

NRZI data encoding and decoding.

•

Bit stuffing and unstuffing.

•

CRC generation and checking.

•

Handshakes.

•

TOKEN type identifying.

•

Address checking.

•

Clock generation (via DPLL).

SIE

DPLL

USB

D+/D-

Buffer

UFI

12MHz

48 MHz +/- 0.25%

D+

Up to 48 MHz

UC_SYSCLK

C51

Microcontroller

Interface

D-

AT89C5122D-RDRUM 数据表(PDF) 94 Page - ATMEL Corporation

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