AT89C5122D-RDRUM datasheet(86/208 Pages) ATMEL

86 / 208 page

AT83R5122, AT8xC5122/23

4202F–SCR–07/2008

Reset Value = 0X10 1111b (default value for a divider by two)

DC/DC Converter

The Smart Card voltage (CVCC) is supplied by the integrated DC/DC converter which is

controlled by several registers:

•

The SCICR register (Table 44 on page 77) controls the CVCC level by means of bits

VCARD[1:0].

•

The SCCON register (Table 45 on page 78) enables to switch the DC/DC converter

on or off by means of bit CARDVCC.

•

The DCCKPS register (Table 61 on page 92) controls the DC/DC clock and current.

The DC/DC converter cannot be switched on while the CPRES pin remains inactive. If

CPRES pin becomes inactive while the DC/DC converter is operating an automatic shut

down sequence of the DC/DC converter is initiated by the electronics.

It is mandatory to switch off the DC/DC Converter before entering in Power-down mode.

Configuration

The DC/DC Converter can work in two different modes which are selected by bit MODE

in DCCKPS register:

•

Pump Mode: an external inductance of 10 μH must be connected between pins LI

and VCC. VCC can be higher or lower than CVCC.

•

Regulator mode : no external inductance is required but VCC must be always higher

than CVCC+0.3V. The Regulation mode will work even if an external inductance of

10 μH is connected between pins LI and VCC

The DC/DC clock prescaler which is controlled by bits DCCKPS[3:0], in DCCKPS regis-

ter must be configured to set the DC/DC clock to a working frequency of 4 MHz which

depends upon the value of the crystal. There is no need to change the default configura-

tion set by the reset sequence if an 8 MHz crystal is used by the application.

The DC/DC Converter implements a current overflow controller which avoids permanent

damage of the DC/DC converter in case of short circuit between CVCC and CVSS. The

maximum limit is around 100 mA. It is possible to increase this limit in normal operating

Table 59.

Smart Card Clock Reload Register - SCICLK (S:C1h, SCRS=1)

543210

XTSCS

SCICLK5

SCICLK4

SCICLK3

SCICLK2

SCICLK1

SCICLK0

Bit Number

Bit Mnemonic

Description

7XTSCS

Smart Card Clock Selection Bit

If XTSCS bit is set OR EXT48 bit is set (in PLLCON register) , CK_PLL is used to generate CK_ISO.

Otherwise, CK_XTAL1 is used to generate CK_ISO.

See the Clock Tree diagram figure 17.

Reserved

The value read from this bit is indeterminate. Do not change these bits.

5 - 0

SCICLK[5:0]

SCIB clock reload register

Prescaler 2 reload value is used to defines the card clock frequency.

If SCICLK[5:0] is smaller than 48 :

Fck_iso = Fck_pll or Fck_XTAL1/ (2 * (48 - SCICLK[5:0]))

If SCICLK[5:0] is equal to 48 :

Fck_iso = Fck_XTAL1

SCICLK[5:0] must be smaller than 49.

AT89C5122D-RDRUM 数据表(PDF) 86 Page - ATMEL Corporation

AT89C5122D-RDRUM 数据表(HTML) 86 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载