AT89C5122D-RDRUM datasheet(71/208 Pages) ATMEL

71 / 208 page

AT83R5122, AT8xC5122/23

4202F–SCR–07/2008

Removal of the smart card will automatically start the power off sequence as described

in Figure 38.

The SCIB deactivation sequence after a reset of the CPU or after a lost of power supply

is ISO7816-3 compliant. The switching order of the signals is the same as in Figure 38

but the delay between signals is analog and not clock dependant.

Figure 38.

SCIB Deactivation Sequence after a Card Extraction

Interrupt Generator

There are several sources of interruption but the SCIB macro-cell issues only one inter-

rupt signal: SCIBIT.

Figure 39.

SCIB Interrupt Sources

This signal is high level active. Each of the sources is able to activate the SCIB interrup-

tion which is cleared when the Smart Card Interrupt register is read by the

microcontroller.

If during the read of the Smart Card Interrupt register another interrupt occurs, the acti-

vation of the corresponding bit in the Smart Card Interrupt register and the new SCIB

interruption is delayed until the interrupt register is read by the microcontroller.

Warning

: Each bit of the SCIIR register is irrelevant while the corresponding interrup-

tion is disabled in SCIER register. When the interruption mode is not used, the bits of

the SCISR register must be used instead of the bits of the SCIIR register.

CVCC

CRST

CCLK

CIO

8 Clock Cycles

ESCTBI

ICARDER

ESCWTI

ESCRI

ESCPI

EVCARDER

Transmit buffer

copied to shift register

Output current

out of range

Output voltage

out of range

Timeout on WT

counter

Complete

transmission

Complete

reception

Parity error

detected

SCIB IT

ESCTI

SCTBI

ICARDERR

VCARDERR

SCWTI

SCTI

SCRI

SCPI

AT89C5122D-RDRUM 数据表(PDF) 71 Page - ATMEL Corporation

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