AT89C5122D-RDRUM datasheet(105/208 Pages) ATMEL

105 / 208 page

105

AT83R5122, AT8xC5122/23

4202F–SCR–07/2008

Control Transactions

Setup Stage

The DIR bit in the UEPSTAX register should be at 0.

Receiving Setup packets is the same as receiving Bulk Out packets, except that the

Rxsetup bit in the UEPSTAX register is set by the USB controller instead of the

RXOUTB0 bit to indicate that an Out packet with a Setup PID has been received on the

Control endpoint. When the RXSETUP bit has been set, all the other bits of the UEP-

STAX register are cleared and an interrupt is triggered if enabled.

The firmware has to read the Setup request stored in the Control endpoint FIFO before

clearing the RXSETUP bit to free the endpoint FIFO for the next transaction.

Data Stage: Control Endpoint

Direction

The data stage management is similar to Bulk management.

A Control endpoint is managed by the USB controller as a full-duplex endpoint: IN and

OUT. All other endpoint types are managed as half-duplex endpoint: IN or OUT. The

firmware has to specify the control endpoint direction for the data stage using the DIR bit

in the UEPSTAX register.

•

If the data stage consists of INs,

the firmware has to set the DIR bit in the UEPSTAX register before writing into the

FIFO and sending the data by setting to 1 the TXRDY bit in the UEPSTAX register.

The IN transaction is complete when the TXCMPL has been set by the hardware.

The firmware should clear the TXCMPL bit before any other transaction.

•

If the data stage consists of OUTs,

the firmware has to leave the DIR bit at 0. The RXOUTB0 bit is set by hardware

when a new valid packet has been received on the endpoint. The firmware must

read the data stored into the FIFO and then clear the RXOUTB0 bit to reset the

FIFO and to allow the next transaction.

The bit DIR is used to send the correct data toggle in the data stage.

To send a STALL handshake, see “STALL Handshake” on page 108.

Status Stage

The DIR bit in the UEPSTAX register should be reset at 0 for IN and OUT status stage.

The status stage management is similar to Bulk management.

•

For a Control Write transaction or a No-Data Control transaction, the status stage

consists of a IN Zero Length Packet (see “Bulk/Interrupt IN Transactions In

Standard Mode” on page 103). To send a STALL handshake, see “STALL

Handshake” on page 108.

•

For a Control Read transaction, the status stage consists of a OUT Zero Length

Packet (see “Bulk/Interrupt OUT Transactions in Standard Mode” on page 101).

AT89C5122D-RDRUM 数据表(PDF) 105 Page - ATMEL Corporation

AT89C5122D-RDRUM 数据表(HTML) 105 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载