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AT89C5122D-RDRUM 数据表(PDF) 162 Page - ATMEL Corporation |
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AT89C5122D-RDRUM 数据表(HTML) 162 Page - ATMEL Corporation |
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162 / 208 page  162 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 Reset Value = X0XX 0XXXb (Bit addressable) Reset Value = X000 0000b (Bit addressable) Table 100. Interrupt Enable Register 1 - IEN1 (B1h) for AT83C5123 7654 3210 -EUSB - - ESCI - Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not change this bit. 6EUSB USB Interrupt Enable bit Cleared to disable USB interrupt . Set to enable USB interrupt. 5 - 4 - Reserved The value read from this bit is indeterminate. Do not change these bits. 3ESCI SCI interrupt Enable bit Cleared to disable SCIinterrupt . Set to enable SCI interrupt. 2 Reserved The value read from this bit is indeterminate. Do not change this bit. 1- Reserved The value read from this bit is indeterminate. Do not change this bit. 0 Reserved The value read from this bit is indeterminate. Do not change this bit. Table 101. Interrupt Priority Low Register 0 - IPL0 (B8h) 7654 3210 - - - PSL PT1L PX1LPT0LPX0L Bit Number Bit Mnemonic Description 7 - 5 - Reserved The value read from this bit is indeterminate. Do not change these bits. 4PSL Serial port Priority bit Refer to PSH for priority level. 3PT1L Timer 1 overflow interrupt Priority bit Refer to PT1H for priority level. 2 PX1L External interrupt 1 Priority bit Refer to PX1H for priority level. 1PT0L Timer 0 overflow interrupt Priority bit Refer to PT0H for priority level. 0 PX0L External interrupt 0 Priority bit Refer to PX0H for priority level. |
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