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数据搜索系统，热门电子元器件搜索 |
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AT89C5122D-RDRUM 数据表(PDF) 176 Page - ATMEL Corporation |
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AT89C5122D-RDRUM 数据表(HTML) 176 Page - ATMEL Corporation |
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176 / 208 page  176 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 Reset Value = XXXX X000b The three lower bits (S0, S1, S2) located into WDTPRG register enables to program the WDT duration. To compute WD Timeout, the following formula must be applied: Time Out = 6 * (214 * 2 Svalue - 1 ) / FCK_WD Note: Svalue represents the decimal value of (S2 S1 S0) Table 109. Watchdog Timer Out Register - WDTPRG (0A7h) 76543210 ----- S2 S1 S0 Bit Number Bit Mnemonic Description 7 - 3 - Reserved The value read from this bit is indeterminate. Do not change these bits. 2 S2 WDT Time-out select bit 2 1 S1 WDT Time-out select bit 1 0 S0 WDT Time-out select bit 0 Table 110. Machine Cycle Count S2 S1 S0 Machine Cycle Count 00 0 214 - 1 00 1 215 - 1 01 0 216 - 1 01 1 217 - 1 10 0 218 - 1 10 1 219 - 1 11 0 220 - 1 11 1 221 - 1 |
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