AD9548SLASHPCBZ datasheet(27/112 Pages) AD

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AD9548

Rev. 0 | Page 27 of 112

REFERENCE CLOCK INPUTS

Four pairs of pins provide access to the reference clock receivers.

Each pair is configurable either as a single differential receiver

or as two independent single-ended receivers. To accommodate

input signals with slow rising and falling edges, both the

differential and single-ended input receivers employ hysteresis.

Hysteresis also ensures that a disconnected or floating input

does not cause the receiver to oscillate spontaneously.

When configured for differential operation, the input receivers

accommodate either ac- or dc-coupled input signals. The

receiver is internally dc biased in order to handle ac-coupled

operation.

When configured for single-ended operation, the input

receivers exhibit a pull-down load of 45 kΩ (typical). Three

user-programmable threshold voltage ranges are available for

each single-ended receiver.

REFERENCE MONITORS

The reference monitors depend on a known and accurate

system clock period. Therefore, the functioning of the reference

monitors is not reliable until the system clock is stable. To avoid

an incorrect valid indication, the reference monitors indicate

fault status until the system clock stability timer expires (see the

System Clock Stability Timer section).

Reference Period Monitor

Each reference input has a dedicated monitor that repeatedly

measures the reference period. The AD9548 uses the reference

period measurements to determine the validity of the reference

based on a set of user provided parameters in the profile

(Register 0600 to Register 07FF) section). The AD9548 also

uses the reference period monitor to assign a particular

reference to a profile when the user programs the device for

automatic profile assignment.

The monitor works by comparing the measured period of a

particular reference input with the parameters stored in the

profile register assigned to that same reference input. The

parameters include the reference period, an inner tolerance, and

an outer tolerance. A 50-bit number defines the reference

period in units of femtoseconds. The 50-bit range allows for a

reference period entry of up to 1.125 sec. However, an actual

reference signal with a period in excess of 1 sec is beyond the

recommended operating range of the device. A

20-bit number defines the inner and outer tolerances. The value

stored in the register is the reciprocal of the tolerance

specification. For example, a tolerance specification of 50 ppm

yields a register value of 1/(50 ppm) = 1/0.000050 = 20,000

(0x04E20).

The use of two tolerance values provides hysteresis for the

monitor decision logic. The inner tolerance applies to a

previously faulted reference and specifies the largest period

tolerance that a previously faulted reference can exhibit before it

qualifies as nonfaulted. The outer tolerance applies to an already

nonfaulted reference. It specifies the largest period tolerance

that a nonfaulted reference can exhibit before being faulted.

To produce decision hysteresis, the inner tolerance must be less

than the outer tolerance. That is, a faulted reference must meet

tighter requirements to become nonfaulted than a nonfaulted

reference must meet to become faulted.

Reference Validation Timer

Each reference input has a dedicated validation timer. The

validation timer establishes the amount of time that a

previously faulted reference must remain fault free before the

AD9548 declares it nonfaulted. The timeout period of the

validation timer is programmable via a 16-bit register (see the

validation register contained within each of the eight profile

registers in the register map, Address 0600 to Address 07FF).

The 16-bit number stored in the validation register represents

units of milliseconds, which yields a maximum timeout period

of 65,535 ms.

Note that a validation period of 0 must be programmed to

disable the validation timer. With the validation timer disabled,

the user must validate a reference manually via the force

validation timeout register (Address 0A0E).

Reference Redetect Timer

Each reference input has a dedicated redetect timer. The

redetect timer is useful only with the device programmed for

automatic profile selection. The redetect timer establishes the

amount of time that a reference must remain faulted before the

AD9548 attempts to reassign it to a new profile. The timeout

period of the redetect timer is programmable via a 16-bit

of the eight profile registers in the register map, Address 0600 to

Address 07FF). The 16-bit number stored in the redetect

timeout register represents units of milliseconds, which yields a

maximum timeout period of 65,535 ms.

Note that a timeout period of 0 must be programmed to disable

the redetect timer.

Reference Validation Override Control

to override the reference validation logic enabling a certain level

of troubleshooting capability. Each of the eight input references

has a dedicated block of validation logic as shown in Figure 34.

The state of the valid signal at the output is what defines a

particular reference as valid (1) or not (0), which includes the

validation period (if activated) as prescribed by the validation

timer. The override controls are the three control bits on the left

side of the diagram.

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